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Product Brief
MPC555PB/D Rev. 3, 2/2003 MPC555 Product Brief
This document provides an overview of the MPC555 microcontroller, including a block diagram showing the major modular components and sections that list the major features. The MPC555 member of the Motorola MPC500 RISC Microcontroller family.
Table 1. MPC555 Features
Device MPC555 Flash 448 Kbytes Code Compression Code compression not supported
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* * * * *
Introduction
PowerPCTM core with floating-point unit 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM 448 Kbytes Flash EEPROM with 5-V programming 5-V I/O system Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B controller modules (TouCANTM) 50-channel timer system: dual time processor units (TPU3), modular I/O system (MIOS1) 32 analog inputs: dual queued analog-to-digital converters (QADC64) Submicron HCMOS (CDR1) technology 272-pin plastic ball grid array (PBGA) packaging 40-MHz operation, -40 C to 125 C with dual supply (3.3 V, 5 V) (-55 C to 125 C for the suffix A device) 32-bit architecture (PowerPC ISA architecture compliant) Core performance measured at 52.7-Kbyte Dhrystones (v2.1) @ 40 MHz Fully static, low power operation Integrated double-precision floating-point unit Precise exception model
The MPC555 device offers the following features:
* * * * * * * * * *
Block Diagram
*
Extensive system development support -- On-chip watchpoints and breakpoints -- Program flow tracking -- BDM on-chip emulation development interface
1.1
Block Diagram
Figure 1 is a block diagram of the MPC555.
192 Kbytes Flash
256 Kbytes Flash Burst Interface
U-bus E-bus
RCPU 16 Kbytes SRAM
USIU 10 Kbytes SRAM
L2U
L-bus
QADC
QADC
QSMCM
UIMB
TouCAN
IMB3
TPU3
DPTRAM
TPU3
TouCAN
MIOS1
Figure 1. MPC555 Block Diagram
1.2
1.2.1
* * *
Key Features
Four-Bank Memory Controller
Works with SRAM, EPROM, Flash EEPROM, and other peripherals Byte write enables 32-bit address decodes with bit masks
The MPC555 key features are explained in the following sections.
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MPC555 Product Brief
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Key Features
1.2.2
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U-Bus System Interface Unit (USIU)
Clock synthesizer Power management Reset controller MPC555 decrementer and time base Real-time clock register Periodic interrupt timer Hardware bus monitor and software watchdog timer Interrupt controller that supports up to eight external and eight internal interrupts IEEE 1149.1 JTAG test access port External bus interface -- 24 address pins, 32 data pins -- Supports multiple master designs -- Four-beat transfer bursts, two-clock minimum bus transactions -- Supports 5V inputs, provides 3.3-V outputs
1.2.3
* * * *
Flexible Memory Protection Unit
Four instruction regions and four data regions 4-Kbyte to 16-Mbyte region size support Default attributes available in one global entry Attribute support for speculative accesses
1.2.4
* * * *
448-Kbyte Flash EEPROM Memory
One 256-Kbyte and one 192-Kbyte module Page read mode Block (32-Kbyte) erasable External 4.75-V to 5.25-V program and erase power supply
1.2.5
* * * *
26-Kbytes of Static RAM
One 16-Kbyte and one 10-Kbyte module Fast (one-clock) access Keep-alive power Soft defect detection (SDD)
1.2.6
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General-Purpose I/O Support
Address (24) and data (32) pins can be used for general-purpose I/O in single-chip mode Nine general-purpose I/O pins in MIOS1 unit Many peripheral pins can be used for general-purpose I/O when not used for primary function 5-V tolerant inputs/outputs
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MPC555 Product Brief
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Key Features
1.2.7
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Two Time Processor Units (TPU3)
Each TPU3 module provides these features: -- A dedicated micro-engine operates independently of the RCPU -- 16 independent programmable channels and pins -- Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare register and a 16-bit comparator -- Nine pre-programmed timer functions are available -- Any channel can perform any time function -- Each timer function can be assigned to more than one channel -- Two timer count registers with programmable prescalers -- Each channel can be synchronized to one or both counters -- Selectable channel priority levels -- 5-V tolerant inputs/outputs
*
6-Kbyte dual port TPU RAM (DPTRAM) is shared by the two TPU3 modules for TPU microcode
1.2.8
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18-Channel Modular I/O System (MIOS1)
Ten double action submodules (DASM) Eight dedicated PWM sub-modules (PWMSM) Two 16-bit modulus counter submodules (MCSM) Two parallel port I/O submodules (PIOSM) 5-V tolerant inputs/outputs
1.2.9
Two Queued Analog-to-Digital Converter Modules (QADC64)
Up to 16 analog input channels, using internal multiplexing Up to 41 total input channels, using internal and external multiplexing 10-bit A/D converter with internal sample/hold Typical conversion time of 10 s (100,000 samples per second) Two conversion command queues of variable length Automated queue modes initiated by: -- External edge trigger/level gate -- Software command
Each QADC provides: * * * * * *
* * *
64 result registers Output data that is right- or left-justified, signed or unsigned 5-V reference and range
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Key Features
1.2.10 Two CAN 2.0B Controller Modules (TouCAN)
Each TouCAN provides these features: * * * * * * * * * * * * * * * Full implementation of CAN protocol specification, version 2.0A and 2.0B Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length Global mask register for message buffers 0 to 13 Independent mask registers for message buffers 14 and 15 Programmable transmit-first scheme: lowest ID or lowest buffer number 16-bit free-running timer for message time-stamping Low power sleep mode with programmable wake-up on bus activity Programmable I/O modes Maskable interrupts Independent of the transmission medium (external transceiver is assumed) Open network architecture Multimaster concept High immunity to EMI Short latency time for high-priority messages Low power sleep mode with programmable wakeup on bus activity
1.2.11 Queued Serial Multi-Channel Module (QSMCM)
* Queued serial peripheral interface (QSPI) -- Provides full-duplex communication port for peripheral expansion or interprocessor communication -- Up to 32 preprogrammed transfers, reducing overhead -- 160-byte queue buffer -- Programmable transfer length: from 8 to 16 bits, inclusive -- Synchronous interface with baud rate of up to system clock divided by 4 -- Four programmable peripheral-select pins support up to 16 devices -- Wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals (e.g., - serial A/D converters, I/O latches, etc.) Two serial communications interfaces (SCI). Each SCI offers these features: -- UART mode provides NRZ format and half-or full-duplex interface -- 16 register receive buffer and 16 register transmit buffer (SCI1 only) -- Advanced error detection and optional parity generation and detection -- Word length programmable as 8 or 9 bits -- Separate transmitter and receiver enable bits and double buffering of data -- Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or a new address byte is received -- External source clock for baud generation -- Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete inputs, allowing realization of a low-speed serial protocol
*
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Key Features
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MPC555 Address Map
0x00 0000 CMF Flash A 256 Kbytes 0x04 0000 0x06 FFFF 0x07 0000 CMF Flash B 192 Kbytes USIU Control Registers 1 Kbyte FLASH Module A (64 b ytes) FLASH Module B (64 b ytes) Reserved for Flash (2.6 Mbytes - 16 Kbytes) Res erved for USIU 0 x 2 F BFFF 0x 2F C000 0 x 2 F FFFF 0x 30 0000 0x2F C800 0x2F C840 0x 2F C880 0x2F C000
The internal memory map is shown in Figure 2.
U SI U & F l a sh Control 1 6 Kbytes IMB3 Address Space UIMB Interface & IMB3 Modules (32 Kbytes) DPTRAM Control (12 bytes) Reserved (8180 bytes) 0x30 2000 DPTRAM (6 Kbytes) Reserved for IMB3 (4 80 Kbytes) Reserved (2 Kbytes) TPU3_A (1 Kbyte) 0x30 4000 0x30 4400 0x30 4800 0x30 4C00 0x30 5000 SR A M C o n t r o l B ( 8 b ytes) QSMCM (4 Kbytes) 0x30 6000 MIOS1 (4 Kbytes) Reserved (485.98 Kbytes) TouCAN_A (1 Kbyte) TouCAN_B (1 Kbyte) SRAM A (10 Kbytes) SRAM B (16 Kbytes) Reserved (1920 bytes) UIMB Registers (128 bytes) 0x30 7080 0x30 7480 0x30 7884 0x30 7F80 0x30 7FFF 0x30 0000
0 x 3 0 7 FFF 0x 30 8000
0 x 3 7 FFFF 0x 3 8 0 00 0 SR A M C o n t r o l A ( 8 bytes) 0x 38 0008
TPU3_B (1 Kbyte) QADC_A (1 Kbyte) QADC_B (1 Kbyte)
0x 38 0010
0x 3F 9800
0x 3F C000 0x 3 F FFFF
Figure 2. MPC555 Internal Memory Map
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MPC555 Product Brief
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MPC555
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A_TPUCH1 A_TPUCH4 A_TPUCH8 A_TPUCH12 A_TPUCH15 VRL AAN0_PQB0 AAN48_PQB4 AAN52_PQA0 AAN54_PQA2 BAN0_PQB0 BAN2_PQB2 BAN3_PQB3 BAN51_PQB7 VDDH MDA11 MDA12 MDA13 VDDH
Ball Map
11 12 13 14 15 16 17 18 19 20
1
3
4
5
6
7
8
9
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VDDH A_TPUCH6 A_TPUCH10 A_TPUCH11 A_TPUCH14 VRH AAN3_PQB3 AAN49_PQB5 AAN53_PQA1 AAN57_PQA5 BAN1_PQB1 BAN48_PQB4 BAN52_PQA0 BAN54_PQA2 ETRIG2 MDA14 MDA15 VDDH MDA28 A_T2CLK A_TPUCH3 A_TPUCH7 A_TPUCH9 A_TPUCH13 VDDA AAN2_PQB2 AAN51_PQB7 AAN56_PQA4 AAN59_PQA7 BAN49_PQB5 BAN53_PQA1 BAN56_PQA4 BAN57_PQA5 ETRIG1 MDA27 MDA29 MDA30 MDA31 A_TPUCH2 A_TPUCH5 VDDI VSSA AAN1_PQB1 AAN50_PQB6 AAN55_PQA3 AAN58_PQA6 BAN50_PQB6 BAN55_PQA3 BAN58_PQA6 BAN59_PQA7 VDDI VDDL MPWM1 MPWM2 MPWM3 B_TPUCH10 B_TPUCH14 VDDL MPWM0 MPWM17 MPWM19 MPIO6 B_TPUCH6 B_TPUCH8 B_TPUCH12 MPWM16 MPWM18 MPIO7 MPIO9 B_TPUCH3 B_TPUCH4 B_TPUCH9 MPIO5 MPIO8 MPIO11 MPIO12 B_TPUCH0 B_CNRX0 B_CNTX0 MPIO10 MPIO15 MPIO14 MPIO13 TDO_ DSDO TRST_B VDD SRAM VSS VSS VSS VSS VF2 _MPIO2 VFLS0 _MPIO3 VF0 _MPIO0 VF1 _MPIO1 TDI_DSDI SGP_FRZ VDDL VSS VSS VSS VSS VDDL VFLS1 _MPIO4 A_CNTX0 A_CNRX0 IRQ3B _SGP VSS VSS VSS VSS IRQ4B _SGP PCS1 _QGP PCS0 _QGP MISO _QGP4 MOSI _QGP5 IRQ1B _SGP SGP_ IRQOUTB VSS VSS VSS VSS IRQ2B _SGP PCS3 _QGP PCS2 _QGP ECK SCK_ QGP6 BRB_IWP2 BGB_LWP1 BBB _IWP3
A
VDDH
B
B_T2CLK
C B_TPUCH15
D B_TPUCH11 B_TPUCH13 A_TPUCH0
E
B_TPUCH7
F
B_TPUCH5
G
B_TPUCH2
Figure 3 shows the pinout for the MPC555.
H
B_TPUCH1
J TCK_ DSCK
K
TMS
MPC555 Pinout Diagram
L
IWP1 _VFLS IWP0 _VFLS
Figure 3. MPC555 Pinout Diagram
MPC555 Product Brief
Note: The pinout is a top down view of the package.
WEB_ AT[2] WEB_ AT[3] CS0B CS3B CS2B CS1B TEAB TSIZ1 VDDL TAB TSB BDIPB VDDI Addr_ SGP31 Addr_ SGP30 Addr_ SGP28 Addr_ SGP29 VDDL Data_ SGP29 Data_ SGP27 Data_ SGP25 Data_ SGP23 BIB_STSB VDDH
M IRQ0B _SGP
N
WEB_ AT[0]
RXD1_ QGPI
TXD1_ QGPO
RXD2_ QGPI
TXD2_ QGPO
P
WEB_ AT[1]
VPP
EPEE
VSSF
VDDH
R
RD_WRB
VDDL
VDDF
XFC
VDDSYN
T
OEB
VDDI
KAPWR
VSSSYN
EXTAL
U
TSIZ0
VDDL
Data_ SGP20 RCFB_TXP
EXTCLK
ECK_ BUCK
XTAL
V
BURSTB
Addr_ SGP11 Addr_ SGP10 Addr_ SGP9 Addr_ SGP8 Addr_ SGP22 Addr_ SGP27 Data_ SGP31 Data_ SGP30 Data_ SGP28 Data_ SGP26 Data_ SGP24 Data_ SGP22 Data_ SGP21 Data_ SGP19 Data_ SGP18
CLKOUT
PORESETB
SRESETB
W Addr_ SGP12
Addr_ SGP14 Addr_ SGP16 Addr_ SGP18 Addr_ SGP20 Addr_ SGP23 Addr_ SGP26 Data_ SGP1 Data_ SGP3 Data_ SGP5 Data_ SGP7 Data_ SGP9 Data_ SGP11 Data_ SGP13 Data_ SGP15 Data_ SGP17 IRQ5B _SGP
VDDH
HRESETB
Y =3 volt power (I/O) VDDi
VDDH
Addr_ SGP13 Addr_ SGP15 Addr_ SGP17 Addr_ SGP19 Addr_ SGP21 Addr_ SGP24 Addr_ SGP25 Data_ SGP0 Data_ SGP2 Data_ SGP4 Data_ SGP6 Data_ SGP8 Data_ SGP10 Data_ SGP12 Data_ SGP14 Data_ SGP16 IRQ6B _mck2 IRQ7B _mck3
VDDH
VDDH
=3 volt power (internal)
VSS
=ground 21 November 1997
VDDH
=5 volt power
=Misc power Version 10.2
Substrate 9/30/97a
Key Features
y Dees
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Key Features
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* * * * * * * * * * * *
Supporting Documentation List
MPC555 User's Manual (MPC555UM/AD) RCPU Reference Manual (RCPURM/AD) Board Strategies for Ensuring Optimum Frequency Synthesizer Performance (AN1282/D) Using the MIOS on the MPC555 Evaluation Board (AN1778/D) Exception Table Relocation and Multi-Processor Address Mapping in the Embedded MPC5XX Family (AN1821/D) Non-Volatile Memory Technology Overview (AN1837/D) Designing Expansion Boards for the Motorola EVB555/ETAS ES200 (AN2001/D) MPC555 Interrupts (AN2109/D) EMC Guidelines for MPC500-Based Automotive Powertrain Systems (AN2127/D) Nexus Standard Specification (non-Motorola document) Nexus Web Site: http://www.nexus5001.org/ IEEE 1149.1 Specification (non-Motorola document)
This list contains references to currently available and planned documentation.
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Revision History
Table 2. Revision History
Revision Number 2 2.1 3 Substantive Changes Existing Document. Added temperature range for suffix A device. Updated template and formats. Date of Release September 2001 11 December 2002 11 February 2003
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Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. The described product contains a PowerPC processor core. The PowerPC name is a trademark of IBM Corp. and used under license. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. (c) Motorola, Inc. 2003
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